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128-bit computing

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Computer architecture bit widths
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Application
Binary floating-point precision
Decimal floating-point precision

In computer architecture, 128-bit integers, memory addresses, or other data units are those that are 128 bits (16 octets) wide. Also, 128-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size.

General home computing and gaming utility emerged at 8-bit word sizes, as 28=256 words, a natural unit of data, became possible. Early 8-bit CPUs (such as the Zilog Z80 and MOS Technology 6502, used in the 1977 PET, TRS-80, and Apple II) inaugurated the era of personal computing. Many 16-bit CPUs already existed in the mid-1970s. Over the next 30 years, the shift to 16-bit, 32-bit and 64-bit computing allowed, respectively, 216 = 65,536 unique words, 232 = 4,294,967,296 unique words and 264 = 18,​446,​744,​073,​709,​551,​616 unique words, each step offering a meaningful advantage until 64 bits was reached. Further advantages evaporate from 64-bit to 128-bit computing as the number of possible values in a register increases from roughly 18 quintillion (1.8×1019) to 340 undecillion (3.4×1038) as so many unique values are never utilized. Thus, with a register that can store 2128 values, no advantages over 64-bit computing accrue to either home computing or gaming. CPUs with a larger word size also require more circuitry, are physically larger, require more power and generate more heat. Thus, there are currently no mainstream general-purpose processors built to operate on 128-bit integers or addresses, although a number of processors do have specialized ways to operate on 128-bit chunks of data, and are given in § History.

Representation

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A processor with 128-bit byte addressing could directly address up to 2128 (over 3.40×1038) bytes, which would greatly exceed the total data captured, created, or replicated on Earth as of 2018, which has been estimated to be around 33 zettabytes (over 274 bytes).[1]

A 128-bit register can store 2128 (over 3.40 × 1038) different values. The range of integer values that can be stored in 128 bits depends on the integer representation used. With the two most common representations, the range is 0 through 340,​282,​366,​920,​938,​463,​463,​374,​607,​431,​768,​211,​455 (2128 − 1) for representation as an (unsigned) binary number, and −170,​141,​183,​460,​469,​231,​731,​687,​303,​715,​884,​105,​728 (−2127) through 170,​141,​183,​460,​469,​231,​731,​687,​303,​715,​884,​105,​727 (2127 − 1) for representation as two's complement.

Quadruple precision (128 bits) floating-point numbers can store 113-bit fixed-point numbers or integers accurately without losing precision (thus 64-bit integers in particular). Quadruple precision floats can also represent any position in the observable universe with at least micrometer precision.[citation needed]

Decimal128 floating-point numbers can represent numbers with up to 34 significant digits.

History

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A 128-bit multicomparator was described by researchers in 1976.[2]

The IBM System/360 Model 85,[3] and IBM System/370 and its successors, support 128-bit floating-point arithmetic.

The Siemens 7.700 and 7.500 series mainframes and their successors support 128-bit floating-point arithmetic.[4]

Most modern CPUs feature single instruction, multiple data (SIMD) instruction sets (Streaming SIMD Extensions, AltiVec etc.) where 128-bit vector registers are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their vector registers have the size of 128 bits.

The DEC VAX supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.

The ICL 2900 Series provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic.

A CPU with 128-bit multimedia extensions was designed by researchers in 1999.[5]

Among the sixth generation of video game consoles, the Dreamcast and the PlayStation 2 used the term 128-bit in their marketing to describe their capability. The Playstation 2's CPU had 128-bit SIMD capabilities.[6][7] Neither console supported 128-bit addressing or 128-bit integer arithmetic.

Hardware

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The RISC-V ISA specification from 2016 includes a reservation for a 128-bit version of the architecture, but the details remain undefined intentionally, because there is yet so little practical experience with such large word size.[8]

Software

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In the same way that compilers emulate e.g. 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the GCC C compiler 4.6 and later has a 128-bit integer type __int128 for some architectures.[9] GCC and compatible compilers signal the presence of 128-bit arithmetic when the macro __SIZEOF_INT128__ is defined.[10] For the C programming language, 128-bit support is optional, e.g. via the int128_t type, or it can be implemented by a compiler-specific extension. The Rust programming language has built-in support for 128-bit integers (originally via LLVM), which is implemented on all platforms.[11] A 128-bit type provided by a C compiler can be available in Perl via the Math::Int128 module.[12]

Uses

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  • Universally unique identifiers (UUID) consist of a 128-bit value.
  • IPv6 routes computer network traffic amongst a 128-bit range of addresses.
  • ZFS is a 128-bit file system.
  • 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography.
  • The IBM i Machine Interface defines all pointers as 128-bit. The Machine Interface instructions are translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware had a CISC instruction set with 48-bit addressing, while current hardware is 64-bit PowerPC/Power ISA. In the PowerPC/Power ISA implementation, the first four bytes contain information used to identify the type of the object being referenced, and the final eight bytes are used as a virtual memory address.[13] The remaining four bytes are unused, and would allow IBM i applications to be extended to 96-bit addressing in future without requiring code changes.
  • Increasing the word size can speed up multiple precision mathematical libraries, with applications to cryptography, and potentially speed up algorithms used in complex mathematical processing (numerical analysis, signal processing, complex photo editing and audio and video processing).
  • MD5 is a hash function producing a 128-bit hash value.
  • Apache Avro uses a 128-bit random number as synchronization marker for efficient splitting of data files.[14][15]

References

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  1. ^ Reinsel, David; Gantz, John; Rydning, John (November 2018). "The Digitalization of the World from Edge to Core" (PDF). Seagate Technology. IDC. p. 3. Archived (PDF) from the original on 7 September 2021. Retrieved 14 September 2021.
  2. ^ Mead, Carver A.; Pashley, Richard D.; Britton, Lee D.; Daimon, Yoshiaki T.; Sando, Stewart F. Jr. (October 1976). "128-Bit Multicomparator" (PDF). IEEE Journal of Solid-State Circuits. 11 (5): 692–695. Bibcode:1976IJSSC..11..692M. doi:10.1109/JSSC.1976.1050799. S2CID 27262034. Archived (PDF) from the original on 3 November 2018.
  3. ^ Padegs A (1968). "Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture". IBM Systems Journal. 7: 22–29. doi:10.1147/sj.71.0022.
  4. ^ Assembler Instructions (BS2000/OSD). 1993.
  5. ^ Suzuoki, M.; Kutaragi, K.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, M.; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Yutaka, T.; Okada, T.; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, A.; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, H.; Ohtaguro, Y.; Aono, A. (November 1999). "A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder". IEEE Journal of Solid-State Circuits. 34 (11): 1608–1618. Bibcode:1999IJSSC..34.1608S. doi:10.1109/4.799870.
  6. ^ Hennessy, John L.; Patterson, David A. (2003). Computer Architecture: A Quantitative Approach (Third ed.). Morgan Kaufmann Publishers. ISBN 1-55860-724-2.
  7. ^ Diefendorff, Keith (19 April 1999). "Sony's Emotionally Charged Chip". Microprocessor Report. 13 (5). Microdesign Resources.
  8. ^ Waterman, Andrew; Asanović, Krste. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2". University of California, Berkeley. EECS-2016-118. Retrieved 25 May 2017.
  9. ^ "GCC 4.6 Release Series – Changes, New Features, and Fixes". Retrieved 25 July 2016.
  10. ^ Marc Glisse (26 August 2015). "128-bit integer – nonsensical documentation?". GCC-Help. Retrieved 23 January 2020.
  11. ^ "i128 – Rust". doc.rust-lang.org. Retrieved 25 June 2020.
  12. ^ "Math::Int128". metacpan.org. Retrieved 25 June 2020.
  13. ^ Frank G. Soltis (1997). Inside the AS/400, Second Edition. Duke Press. ISBN 978-1-882419-66-1.
  14. ^ Kleppmann, Martin (24 January 2013). "Re: Synchronization Markers". Archived from the original on 27 September 2015.
  15. ^ "Apache Avro 1.8.0 Specification". Apache Software Foundation.
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